The present invention related generally to differential output and more particularly to providing differential output signals with low skew using single-ended drivers.
With the increasing speed of memory devices, many memory interface protocols adopted differential input/output standards, such as differential SSTL and HSTL, for the data strobe signals. Differential signaling is a method of transmitting information over pairs of wires as opposed to single-ended signaling, which transmits information over single wires. Differential signaling reduces the noise on a connection by rejecting common-mode interference.
In differential signaling, two wires are routed in parallel, and sometimes twisted together, so that they will receive the same interference. One wire carries the signal, and the other wire carries the inverse of the signal, so that the sum of the voltages on the two wires is always constant. Examples include Firewire, SSTL, HSTL, and Serial ATA. A drawback of differential signaling is that it requires two wires for every signal, which has consequences for circuitry involved in outputting the signal.
Output cells typically use a differential driver to provide such differential signals. However, for programmable logic devices (PLD) both single-ended and differential output may be desired. Providing such programmable output capabilities can cause high capacitance on the output pins and/or large skew between the two signals during a differential output.
It is therefore desirable to provide circuits and methods that can output single-ended and differential signals with low pin capacitance, while having a low skew between the differential signals.